Autonomous Chip Design Agents Arrive at DAC 2026

Autonomous chip design agents are long-running AI agents that plan and execute a full engineering workflow, such as chip verification, without step-by-step prompting. Synopsys, Cadence and Siemens each announced one in the two weeks around DAC 2026. None are generally available yet.

TL;DR: In the space of two weeks around the 63rd Design Automation Conference, all three major EDA vendors moved their AI agents from "assist the engineer on one task" to "run the whole loop." Synopsys unveiled a fully autonomous design verification agent it says delivers up to 50X faster time-to-validated RTL¹. Cadence added a fourth AI Super Agent, which it says completes a portfolio spanning silicon to circuit board². Siemens made the sharpest version of the argument all three are converging on: it is not selling autonomy, it is selling self-verifying autonomy, where agents must clear every decision with a deterministic physics engine before proceeding³. Every headline number is vendor-reported against a vendor-chosen baseline, and every product is pre-general-availability. But the underlying pattern matters far beyond chip design.

What You'll Learn

• What Synopsys, Cadence and Siemens each announced, and the date each announcement actually landed
• How a fully autonomous design verification agent is structured, in the vendors' own descriptions
• What "self-verifying agent" means and why Siemens made it the centre of its pitch
• Why electronic design automation got long-running agent autonomy before most software domains
• How to read the 50X, 20X and 15X claims with their baselines attached
• Which "first" and "only" claims survive scrutiny, and the qualifier each one depends on
• What the deterministic-oracle pattern means for agents you build outside chip design

What Was Actually Announced, and When

DAC 2026, the 63rd ACM/EDAC/IEEE Design Automation Conference, ran July 26 to 29 at the Long Beach Convention Center in California⁴. Four separate announcements make up this story, and the sequence is worth getting right because several news aggregators have already collapsed them into a single "at DAC" event.

July 16, San Jose — Cadence introduced the AuraStack AI Super Agent for PCB and advanced packaging design. This was ten days before DAC opened, not at the show².

July 26, Sunnyvale — Synopsys announced fully autonomous, long-running agentic workflows for chip and electronics system design, headlined by the design verification agent¹.

July 26, Plano — Siemens announced an expanded NVIDIA partnership built around self-verifying agentic AI workflows in its Fuse EDA AI Agent system³.

July 27 — Synopsys followed with a second release: autonomous EDA workflows running on Microsoft Discovery, developed with Microsoft and under active evaluation by AMD⁵.

Underneath all four sits the same supplier. On July 26 NVIDIA expanded its Agent Toolkit with PhysicsNeMo and CUDA-X libraries as agent-ready tools, naming Cadence, Siemens, Synopsys, Samsung, ChipAgents, Silvaco, Keysight and TSMC among the companies building on it⁶. Writing for Futurum on July 29, research director Brendan Burke called it "the moment agentic chip design crossed from task assistance to long-running autonomy across all three EDA leaders at once"⁷.

Synopsys: A Verification Agent That Runs the Whole Loop

Synopsys' design verification agent is the clearest illustration of what "long-running" means in practice. According to the company, an orchestrator agent "deconstructs DV goals from specification, design, test repository, and user inputs, and orchestrates specialized agents and tools in a closed loop workflow spanning the full chip verification lifecycle, from test plan generation to coverage closure and advanced debug"¹.

That is a textbook agentic loop: a goal decomposed from source documents, a planner, specialised sub-agents, deterministic tools, and iteration until a measurable target (coverage closure) is met. The claimed result is up to 50X faster time-to-validated RTL with an additional 20 percent coverage improvement, which Synopsys describes as compressing "weeks of manual labor into hours of agentic execution"¹.

The stack is worth noting for anyone tracking who supplies what in agentic infrastructure. Synopsys built on its own AgentEngineer technology plus NVIDIA's Agent Toolkit, the Nemotron 3 Ultra open model, and the OpenShell runtime¹. That same OpenShell runtime appears in all three vendors' announcements: Siemens calls it a secure runtime providing "enterprise-grade security, access controls and audit trails within governed runtime environments"³, and Cadence describes it as "a sandboxed environment for autonomous agents that enforces governance and helps protect sensitive IP through policy controls, isolation and managed access"⁸. That makes NVIDIA the de facto common substrate across competitors.

Synopsys paired this with breadth: its first fully autonomous computer-aided engineering workflow for electronics thermal analysis, built on Ansys Icepak and the open-source PyAEDT libraries, autonomous analog and mixed-signal workflows claiming up to 3X productivity gains, and more than 20 GPU-enabled EDA and multiphysics products including an 18X PrimeSim SPICE speedup¹.

The July 27 follow-up matters strategically. Synopsys put two autonomous workflows on Microsoft Discovery, a debug closure workflow and an implementation and closure workflow, with early evaluations showing 25 to 40 percent reductions in debug cycle time⁵. In Futurum's reading, that leaves Synopsys as the only one of the three running credible agentic workflows on two compute platforms⁷.

Worth noting how the customer describes it. AMD Corporate Fellow Alex Starr, quoted in Synopsys' own release, calls these "AI-assisted design workflows that augment human ingenuity with intelligent automation and optimization"⁵. The vendor says autonomous; the chipmaker evaluating it says AI-assisted. AMD is evaluating, not committed.

Cadence: Completing the Silicon-to-System Agent Stack

Cadence's move is architectural rather than technical. AuraStack joins three earlier AI Super Agents: ChipStack for verification, plus ViraStack "for custom and analog design" and InnoStack "for digital implementation and signoff," both introduced at CadenceLIVE in April 2026 alongside AgentStack as the orchestration framework⁸. Cadence says the fourth agent makes it "the only provider with agentic AI solutions spanning the full electronic system design flow"².

AuraStack itself coordinates domain-specific agents across planning, implementation and multiphysics analysis, running on NVIDIA Blackwell and CUDA-X. Cadence claims 2X faster time to market and 15X higher productivity, and NVIDIA's Tim Costa is quoted in the release saying AuraStack plus the Millennium M2000 supercomputer deliver up to 20X faster multiphysics performance².

Cadence also supplies the most useful vocabulary in this space, describing design autonomy in numbered levels. At Computex 2026 it announced ChipStack reaching Level 5, in a release its own newsroom dates June 1, 2026⁸. The distinction between the top two levels is the part worth borrowing. At Level 4, a super agent handles an atomic request end to end, but the engineer interprets the results and decides what happens next; Level 5 is characterised by loop-level reasoning, where the agent manages the entire validation and iteration cycle⁹. Cadence's release describes the system as evaluating intermediate results, determining next actions and iterating toward closure across specification understanding, RTL generation, verification planning, formal analysis, simulation, debug and design convergence⁸.

Read that closely and the human is still there. Cadence's own framing says engineers can "inspect, guide and collaborate as needed"⁸, and Embedded.com's reporting on the launch concludes that human engineers "will continue to have the ultimate authority over defining the underlying design intent, verifying system-level quality, reviewing proposed code patches, and making final sign-off decisions"⁹. Full autonomy on this scale means the agent does not need a prompt for every step, not that nobody is watching. Level-5 ChipStack and the AgentStack orchestration framework are slated for early-access customers in the second half of 2026⁸.

Siemens: Making the Agent Prove Its Own Work

Siemens' agents are "self-verifying": long-running, domain-scoped agents that "reason, act and continuously validate decisions against deterministic, physics-based EDA engines"³. In other words, the agent cannot advance on its own say-so. A signoff-grade physics tool has to agree first. Futurum called this the most distinctive intellectual position at DAC, summarising it as autonomy not being the goal, trusted autonomy being the goal⁷.

Siemens is not alone in the argument, only the most explicit about it. Cadence made a version of the same case in June, saying autonomous agent behaviour is "tightly coupled with the company's core physics-based design and verification engines," which "keeps AI-directed actions grounded in proven computational models and signoff-accurate results"⁸. Synopsys' partner NVIDIA framed it the same way at DAC, describing agents that "verify their own work"¹. The convergence is the story, not the differentiation.

Amit Gupta, Siemens EDA's chief AI strategy officer, framed the goal as enabling agents "to continuously validate their decisions against proven engineering tools"³. NVIDIA's Timothy Costa put the same idea more bluntly in the Siemens release: "AI agents need trusted tools to reason, act and verify their work"³.

The supporting numbers are narrower than Synopsys' and Cadence's, which is arguably to Siemens' credit. Agentic workflows in the Solido Characterization Suite are reported to cut library characterization turnaround by more than 10X while reducing token costs by 5X to 10X³. That token-cost figure is the kind of detail that rarely appears in agent marketing and connects directly to a problem we have covered before in why AI agent token costs behave so differently from raw model pricing.

Siemens also supplies the industry context for why verification is the beachhead: it says verification consumes up to 70 percent of design time and complexity³.

One caution on the customer proof. STMicroelectronics' non-volatile memory design manager is quoted praising the new Solido Layout Analyzer, but his statement ends "We are planning to test and validate the advantages in our on-going design activity"³. That is an intention, not a deployed production result, and it should be read that way.

Why Chip Design Got Autonomous Agents First

Here is the part that generalises. The hardest unsolved problem in agentic AI is not planning or tool calling. It is verification: knowing whether a long-running agent's output is actually correct without a human reading every line of it. Anthropic's guidance on evaluating agents puts the preference plainly, recommending "deterministic graders where possible, LLM graders where necessary or for additional flexibility, and using human graders judiciously"¹⁰. It also explains why coding agents were early beneficiaries: "Deterministic graders are natural for coding agents because software is generally straightforward to evaluate: does the code run and do the tests pass?"¹⁰

Most agent domains have no such grader. There is no simulator that tells you whether a support reply was good, whether a sales email was on-brand, or whether a research summary omitted the crucial caveat. You fall back to model-based grading, which the same guidance flags as non-deterministic, more expensive than code, and in need of calibration against human graders¹⁰.

Electronic design automation is the rare domain where that deterministic grader, the oracle the agent can appeal to, already exists, is trusted, and has decades of engineering behind it. Simulators, formal analysis, design rule checkers, timing signoff and physics solvers already decide whether a design is manufacturable. They existed long before the agents did, and they were built precisely to catch expensive mistakes before silicon.

That converts the industry's hardest agent problem into a tool call. An agent can propose a change, run the checker, read a pass or fail, and iterate. Coverage closure is a numeric target, so "am I done?" has an answer. This is why Synopsys can point an orchestrator at coverage closure and let it run, and why Siemens can build a product around the agent checking its own work.

Futurum's Burke made a related point about credibility: hardware engineers "treat autonomy-level labels as marketing until proven, and grounding agent decisions in signoff-grade physics engines is the most credible answer yet to that skepticism"⁷. The tools were always the moat. The agents are the new interface to them, which is also the argument behind our earlier look at how many tools an agent can actually juggle before reliability degrades.

Read the Numbers With Their Baselines Attached

Every performance figure in this story is vendor-reported. Futurum labels them "company-disclosed," "company-supplied" and "company-reported" throughout its analysis, and notes that NVIDIA's claim that Nemotron 3 Ultra leads open models in agentic RTL coding is "a vendor-run result awaiting independent replication"⁷. Here is what each headline number is actually measured against.

The pattern is consistent: none of these agents is generally available. Synopsys says customers are "currently evaluating" with availability planned for the second half of 2026¹. Cadence says AuraStack "will be available in 2026"². Siemens says its capabilities "will be available in forthcoming releases"³. NVIDIA's own release carries the plainest version, in its legal boilerplate: "Many of the products and features described herein remain in various stages and will be offered on a when-and-if-available basis"⁶. Futurum's watch list asks whether Synopsys' H2 2026 general availability "arrives with named customers and audited baselines behind the 50x verification claim"⁷.

One number is worth flagging because the two companies announcing it disagree. Siemens says its Solido agentic workflows achieve "over a 5X to 10X reduction in token costs"³. NVIDIA's release, describing the same workflows, says they reduce token costs "by more than 10x"⁶. The table above uses Siemens' figure, since Siemens owns the product. It is a small discrepancy, and a useful reminder that partner press releases can round in a partner's favour.

That is not a reason to dismiss the announcements. It is a reason to treat the numbers as directional until third parties reproduce them, the same discipline we applied when Slack published 200 runs of real agentic testing data.

Every "First" Here Is a Scoped First

Four separate priority claims appear across these releases, and each is defensible only inside its own qualifier.

• Cadence calls AuraStack "the world's first agentic AI platform for printed circuit board (PCB) and advanced packaging design"². The qualifier is the domain: PCB and advanced packaging specifically, not chip design broadly.
• Cadence says it is "now the only provider with agentic AI solutions spanning the full electronic system design flow"². This is a portfolio-coverage claim measured against a flow Cadence itself defines.
• Cadence titled its Level-5 announcement "Industry's First Fully Autonomous Virtual Engineer for Chip Design"⁸. That rests on Cadence's own numbered autonomy scale, a vendor framework rather than an industry standard.
• Synopsys headlines "Industry's First Autonomous EDA Workflows on Microsoft Discovery"⁵. The qualifier is the platform: first on Discovery, a single cloud research environment.

Each is defensible as written. All of them are narrower than a headline makes them sound, and none of them establishes an overall leader. Futurum's read is that the three vendors are making different strategic bets rather than competing on one axis: Synopsys on breadth plus depth, Cadence on architectural completeness, Siemens on trusted autonomy⁷.

What This Means If You Don't Design Chips

The transferable lesson from autonomous chip design agents is not that chip design is ahead. It is that agent autonomy scales with the quality of the verifier, not the quality of the model.

If you are building agents in a domain without a deterministic oracle, the practical move is to manufacture one. That means finding or building the strictest machine-checkable constraint your task allows and putting it inside the loop rather than after it: a type checker, a test suite, a schema validator, a linter, a database constraint, a policy engine, a reconciliation query that must balance. Anything that returns an unambiguous pass or fail turns "did the agent do it right?" from a judgement call into a tool result the agent can act on by itself.

Siemens' framing is the one to steal. The interesting design question is not how much autonomy you can grant, but what your agent must prove, to what, before it is allowed to continue. All three major EDA vendors just bet their agent roadmaps on that answer.

Bottom Line

Something changed in the last two weeks of July 2026: three direct competitors all arrived at long-running agent autonomy in the same window, on a shared NVIDIA substrate. Futurum's framing of the demand side is the part worth keeping, that NVIDIA and AMD have become "the lead customers pulling the roadmaps forward" rather than the vendors pushing⁷. That is a real signal.

What has not changed is the evidence standard. As of publication nothing is generally available, no figure in these releases has been independently reproduced, and every superlative in the coverage carries a qualifier that the headline drops. Read the announcements as a credible direction of travel and a genuinely useful architectural lesson, not as shipped, benchmarked capability.

The lesson is the durable part. Chip design did not get autonomous agents because chip designers had better models. It got them because chip design already had something almost nobody else does: a trusted machine that can tell an agent, cheaply and unambiguously, that it is wrong.